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AS2842/3/4/5
Features Description
The AS2842 family of control ICs provide pin-for-pin replacement of the industry standard UC3842 series of devices. The devices are redesigned to provide significantly improved tolerances in power supply manufacturing. The 2.5 V reference has been trimmed to 1.0% tolerance. The oscillator discharge current is trimmed to provide guaranteed duty cycle clamping rather than specified discharge current. The circuit is more completely specified to guarantee all parameters impacting power supply manufacturing tolerances. In addition, the oscillator and flip-flop sections have been enhanced to provide additional performance. The R T/CT pin now doubles as a synchronization input that can be easily driven from open collector/open drain logic outputs. This sync input is a high impedance input and can easily be used for externally clocked systems. The new flip-flop topology allows the duty cycle on the AS2844/5 to be guaranteed between 49 and 50%. The AS2843/5 requires less than 0.5 mA of start-up current over the full temperature range.
Current Mode Controller
* * * * * *
2.5 V bandgap reference trimmed to 1.0% and temperature-compensated Extended temperature range from - 40 to 105 C AS2842/3 oscillations trimmed for precision duty cycle clamp AS2844/5 have exact 50% max duty cycle clamp Advanced oscillator design simplifies synchronization Improved specs on UVLO and hysteresis provide more predictable start-up and shutdown Improved 5 V regulator provides better AC noise immunity Guaranteed performance with current sense pulled below ground Over-temperature shutdown
* * *
Ordering Information
Description Temperature Range Order Codes
8-Pin Plastic DIP 8-Pin Plastic SOIC
-40 to 105 C -40 to 105 C
AS2842/3/4/5N AS2842/3/4/5D-8
Pin Configuration --
PDIP (N)
COMP VFB ISENSE RT/CT 1 2 3 4
Top view
8L SOIC (D)
8 7 6 5 VREG VCC OUT GND
COMP VFB ISENSE RT/CT
1 2 3 4
8 7 6 5
VREG VCC OUT GND
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AS2842/3/4/5
Functional Block Diagram
1 COMP + 2 VFB - ERROR AMP (1.0 V) R 2R (5.0 V)
Current Mode Controller
5V REGULATOR (2.5 V) REF OK (4 V) UVLO (4 V) 7 VCC (5.0 V) 8 VREG
PWM COMPARATOR 3 ISENSE (3.0 V) -
- S + R
FF PWM LOGIC 6 OUT
(5 V)
CLK / 2 [3844/45] CLK [3842/43] FF S FF T 5 GND
(1.3 V)
(0.6 V)
Figure 1. Block Diagram of the AS2842/3/4/5
Pin Function Description
Pin Number Function Description
1 2 3 4
COMP VFB ISENSE RT/CT
This pin is the error amplifier output. Typically used to provide loop compensation to maintain VFB at 2.5 V. Inverting input of the error amplifier. The non-inverting input is a trimmed 2.5 V bandgap reference. A voltage proportional to inductor current is connected to the input. The PWM uses this information to terminate the gate drive of the output. Oscillator frequency and maximum output duty cycle are set by connecting a resistor (RT) to VREG and a capacitor (CT) to ground. Pulling this pin to ground or to VREG will accomplish a synchronization function. Circuit common ground, power ground, and IC substrate. This output is designed to directly drive a power MOSFET switch. This output can sink or source peak currents up to 1A. The output for the AS2844/5 switches at one-half the oscillator frequency. Positive supply voltage for the IC. This 5 V regulated output provides charging current for the capacitor CT through the resistor RT.
5 6
GND OUT
7 8
VCC VREG
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4 RT/CT
+ + - - OSCILLATOR OVER TEMPERATURE R
38
Current Mode Controller
Absolute Maximum Ratings
Parameter Symbol
AS2842/3/4/5
Rating Unit
Supply Voltage (ICC < 30 mA) Supply Voltage (Low Impedance Source) Output Current Output Energy (Capacitive Load) Analog Inputs (Pin 2, Pin 3) Error Amp Sink Current Maximum Power Dissipation 8L SOIC 8L PDIP Maximum Junction Temperature Storage Temperature Range Lead Temperature, Soldering 10 Seconds
VCC VCC IOUT
Self-Limiting 30 1 5 - 0.3 to 30 10 750 1000
V V A J V mA mW mW C C C
PD
TJ TSTG TL
150 - 65 to 150 300
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Conditions
Parameter Symbol Rating Unit
Typical Thermal Resistances
Package JA JC Typical Derating
Supply Voltage AS2842,4 AS2843,5 Oscillator
VCC 15 10 fOSC 50 to 500 V V kHz
8L PDIP 8L SOIC
95 C/W 175 C/W
50 C/W 45 C/W
10.5 mW/C 5.7 mW/C
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AS2842/3/4/5
Electrical Characteristics
Current Mode Controller
Electrical characteristics are guaranteed over full junction temperature range (-40 to 105 C ). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V RT = 10 k, and CT = 3.3 nF, unless otherwise , stated. To override UVLO, VCC should be raised above 17 V prior to test. Parameter 5 V Regulator Output Voltage Line Regulation Load Regulation Temperature Stability
1 1
Symbol
Test Condition
Min
Typ
Max
Unit
VREG PSRR
TJ = 25 C, IREG = 1 mA 12 VCC 25 V 1 IREG 20 mA
4.95
5.00 2 2 0.2
5.05 10 10 0.4 5.15
V mV mV mV/C V mV V
TCREG Line, load, temperature Over 1,000 hrs at 25 C VNOISE ISC 10 Hz f 100 kHz, TJ = 25 C 30 4.85
Total Output Variation Long-term Stability
1
5 50 100
25
Output Noise Voltage Short Circuit Current 2.5 V Internal Reference Nominal Voltage Line Regulation Load Regulation Temperature Stability
1 1
180
mA
VFB PSRR
T = 25 C; IREG = 1 mA 12 V VCC 25 V 1 IREG 20 mA
2.475
2.500 2 2 0.1
2.525 5 5 0.2 2.550 12
V mV mV mV/C V mV
TCVFB Line, load, temperature Over 1,000 hrs at 125 C 2.450
Total Output Variation Long-term Stability Oscillator Initial Accuracy Voltage Stability Temperature Stability Amplitude Upper Trip Point Lower Trip Point Sync Threshold Discharge Current Duty Cycle Limit
1
2.500 2
fOSC
TJ = 25 C 12 V VCC 25 V
47
52 0.2 5 1.6 2.9 1.3
57 1
kHz % % V V V
1
TCf fOSC VH VL VSYNC ID
TMIN TJ TMAX VRT/CT peak-to-peak
400 7.5 RT = 680 , CT = 5.3 nF, TJ = 25 C 46
600 8.7 50
800 9.5 52
mV mA %
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Current Mode Controller
Electrical Characteristics
(cont'd)
AS2842/3/4/5
Electrical characteristics are guaranteed over full junction temperature range (-40 to 105 C ). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V RT = 10 k, and CT = 3.3 nF, unless otherwise stated. , To override UVLO, VCC should be raised above 17 V prior to test. Parameter Error Amplifier Input Voltage Input Bias Current Voltage Gain Transconductance Unity Gain Bandwidth
1
Symbol VFB IBIAS AVOL Gm GBW PSRR ICOMPL ICOMPH VCOMPH VCOMPL
Test Condition TJ = 25 C
Min 2.475
Typ 2.50 - 0.1
Max 2.525 -1
Unit V A dB mA/mV MHz dB mA mA V
2 VCOMP 4 V
65
90 1
0.8 12 VCC 25 V VFB = 2.7 V, VCOMP = 1.1V VFB = 2.3 V, VCOMP = 5 V VFB = 2.3 V, RL = 15 k to Ground VFB = 2.7 V, RL = 15 k to Pin 8 -0.2 VSENSE 0.8 V VSENSE = 0 V VCOMP = 5 V 0.9 60 2 0.5 5
1.2 70 6 0.8 5.5 0.7 1.1
Power Supply Rejection Ratio Output Sink Current Output Source Current Output Swing High Output Swing Low Current Sense Comparator Transfer Gain2,3 ISENSE Level Shift
2 2
V
AVCS VLS
2.85
3.0 1.5 1 70 -1 85
3.15
V/V V
Maximum Input Signal
1.1
V dB
Power Supply Rejection Ratio Input Bias Current Propagation Delay to Output Output Output Low Level
1
PSRR IBIAS tPD
12 VCC 25 V
-10 150
A ns
VOL VOL
ISINK = 20 mA ISINK = 200 mA ISOURCE = 20mA ISOURCE = 200mA CL = 1 nF CL = 1 nF 13 12
0.1 1.5 13.5 13.5 50 50
0.4 2.2
V V V V
Output High Level
VOH VOH
Rise Time Fall Time
1
tR tF
150 150
ns ns
1
Housekeeping Start-up Threshold VCC(on) 2842/4 2843/5 Minimum Operating Voltage After Turn On Output Low Level in UV State Over-Temperature Shutdown
4
15 7.8 9 7.0
16 8.4 10 7.6 1.5 125
17 9.0 11 8.2 2.0
V V V V V C
VCC(min)
2842/4 2843/5
VOUV TOT
ISINK = 20 mA, VCC = 6 V
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AS2842/3/4/5
Electrical Characteristics
(cont'd)
Current Mode Controller
Electrical characteristics are guaranteed over full junction temperature range (-40 to 105 C ). Ambient temperature must be derated based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V RT = 10 k, and CT = 3.3 nF, unless otherwise stated. , To override UVLO, VCC should be raised above 17 V prior to test. Parameter PWM Maximum Duty Cycle Minimum Duty Cycle Maximum Duty Cycle Minimum Duty Cycle Supply Current Start-up Current Operating Supply Current VCC Zener Voltage ICC ICC VZ ICC = 25 mA 2842/4, VFB = VSENSE = 0 V, VCC = 14 V 2843/5, VFB = VSENSE = 0 V, VCC = 7 V 0.5 0.3 9 30 1.0 0.5 17 mA mA mA V Dmax Dmin Dmax Dmin 2842/3 2842/3 2844/5 2844/5 49 49.5 94 97 100 0 50 0 % % % % Symbol Test Condition Min Typ Max Unit
Notes: 1. This parameter is not 100% tested in production. 2. Parameter measured at trip point of PWM latch. 3. Transfer gain is the relationship between current sense input and corresponding error amplifier output at the PWM latch trip point and is mathematically expressed as follows:
A=
I COMP
VSENSE
; - 0.2 VSENSE 0.8 V
4. At the over-temperature threshold, TOT, the oscillator is disabled. The 5 V reference and the PWM stages, including the PWM latch, remain powered.
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Current Mode Controller
Typical Performance Curves
AS2842/3/4/5
Supply Current vs Supply Voltage
25
25
Output Voltage vs Supply Voltage
20
20
ICC - Supply Current (mA)
15
VOUT - Output Voltage (V)
15
10
10
0 0 5 10 25 20 15 VCC - Supply Voltage (V) 30 35
0 0 5 10 15 20 VCC - Supply Voltage (V) 25 30
Figure 2
AS2843/5
Figure 3
Regulator Output Voltage vs Ambient Temperature
5.04 5.02 IREG - Regulator Short Circuit (mA) VREG - Regulator Output (V)
180
Regulator Short Circuit Current vs Ambient Temperature
140
5.00 4.98 4.96
120
100
80
4.94
4.92
60
4.90 -60
-30
120 0 90 60 30 TA - Ambient Temperature (C) Figure 4
150
40 -60
-30
0 90 120 30 60 TA - Ambient Temperature (C)
AS2842/4
5
AS2843/5
AS2842/4
5
150
Figure 5
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AS2842/3/4/5
Typical Performance Curves
Current Mode Controller
Regulator Load Regulation
0
Maximum Duty Cycle vs Timing Resistor
100
VREG - Regulator Voltage Change (mV)
-4 Maximum Duty Cycle (%)
80
-8
-12 150 C -16 25 C -55 C
60
40
-20
-24 0 20 40 100 120 60 80 ISC - Regulator Source Current (mA) 140
20 0.3 1 3 RT - Timing Register (k)
Figure 7
10
Figure 6
Timing Capacitor vs Oscillator Frequency
100
100
Maximum Duty Cycle Temperature Stability
RT = 10 k
RT = 680 CT - Timing Capacitor (nF) Maximum Duty Cycle (%) 10
90
80
RT = 2.2 k
RT = 1 k RT = 2.2 k 1 RT = 4.7 k RT = 10 k
70 RT = 1 k
60
50
RT = 680
0.1 10 100 FOSC - Oscillator Frequency (kHz) Figure 8 1M
40 -55 -35 -15
5 25 65 85 45 TA - Ambient Temperature
105
125
Figure 9
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Current Mode Controller
Typical Performance Curves
AS2842/3/4/5
Current Sense Input Threshold vs Error Amp Output Voltage
1.2
VSENSE - Current Sense Input Threshold (V)
Error Amp Input Voltage vs Ambient Temperature
2.510
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 1 3 5 2 4 VCOMP - Error Amp Output Voltage (V)
Figure 10
VFB - Error Amp Input Voltage (V)
2.500
TA = 125 C TA = 25 C
2.490
2.480
TA = -55 C
2.470 VFB = VCOMP VCC = 15 V
6
2.460 -60
-30
60 120 0 30 90 TA - Ambient Temperature (C)
Figure 11
150
Output Sink Capability In UnderVoltage Mode
1A VCC = 6 V TA = 25 C
Output Saturation Voltage
0 TJ = 125 C VSAT - Output Saturation Voltage (V) -1 Source Saturation VOUT - VCC
IOUT - Output Sink Current (mA)
100
-2 TJ = -55 C 3 TJ = 25 C
10
2
1
Sink Saturation
TJ = 125 C
1 0 0.5 1 1.5 VOUT - Output Voltage (V) 2 2.5
0 10 100 IOUT - Output Saturation Current (mA) Figure 13 500
Figure 12
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AS2842/3/4/5
Application Information
The AS2842/3/4/5 family of current-mode control ICs are low cost, high performance controllers which are pin compatible with the industry standard UC2842 series of devices. Suitable for many switch mode power supply applications, these ICs have been optimized for use in high frequency off-line and DC-DC converters. The AS2842 has been enhanced to provide significantly improved performance, resulting in exceptionally better tolerances in power supply manufacturing. In addition, all electrical characteristics are guaranteed over the full 0 to 105 C temperature range. Among the many enhancements are: a precision trimmed 2.5 volt reference (0.5% of nominal at the error amplifier input), a significantly reduced propagation delay from current sense input to the IC output, a trimmed oscillator for precise duty-cycle clamping, a modified flip-flop scheme that gives a true 50% duty ratio clamp on 2844/45 types, and an improved 5 V regulator for better AC noise immunity. Furthermore, the AS2842 provides guaranteed performance with current sense input below ground. The advanced oscillator design greatly simplifies synchronization. The device is more completely specified to guarantee all parameters that impact power supply manufacturing tolerances. V
DC
Current Mode Controller
Section 1-- Theory of Operation The functional block diagram of the AS2842 is shown in Figure 1. The IC is comprised of the six basic functions necessary to implement current mode control; the under voltage lockout; the reference; the oscillator; the error amplifier; the current sense comparator/PWM latch; and the output. The following paragraphs will describe the theory of operation of each of the functional blocks. 1.1 Undervoltage lockout (UVLO) The undervoltage lockout function of the AS2842 holds the IC in a low quiescent current ( 1 mA) "standby" mode until the supply voltage (V CC) exceeds the upper UVLO threshold voltage. This guarantees that all of the IC's internal circuitry are properly biased and fully functional before the output stage is enabled. Once the IC turns on, the UVLO threshold shifts to a lower level (hysteresis) to prevent VCC oscillations. The low quiescent current standby mode of the AS2842 allows "bootstrapping" -- a technique used in off-line converters to start the IC from the rectified AC line voltage initially, after which power to the IC is provided by an auxiliary winding off the power supply's main transformer. Figure 14 shows a typical bootstrap circuit where capacitor
>1 mA R VDC MIN 1 mA AS284x 7 VCC IC ENABLE AC LINE 5 GND 16 V/10 V (2842/4) 8.4 V/7.8 V (2843/5) OUT 6 PRI SEC
R<
+ C
+
AUX
Figure 14. Bootstrap Circuit
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Current Mode Controller
(C) is charged via resistor (R) from the rectified AC line. When the voltage on the capacitor (V CC) reaches the upper UVLO threshold, the IC (and hence, the power supply) turns on and the voltage on C begins to quickly discharge due to the increased operating current. During this time, the auxiliary winding begins to supply the current necessary to run the IC. The capacitor must be sufficiently large to maintain a voltage greater than the lower UVLO threshold during start up. The value of R must be selected to provide greater than 1 mA of current at the minimum DC bus voltage (R < VDCmin/1 mA). The UVLO feature of the AS2842 has significant advantages over standard 2842 devices. First, the UVLO thresholds are based on a temperature compensated band gap reference rather than conventional zeners. Second, the UVLO disables the output at power down, offering additional protection in cases where VREG is heavily decoupled. The UVLO on some 2842 devices shuts down the 5 volt regulator only, which results in eventual power down of the output only after the 5 volt rail collapses. This can lead to unwanted stresses on the switching devices during power down. The AS2842 has two separate comparators which monitor both VCC and VREF and hold the output low if either are not within specification. The AS2842 family offers two different UVLO options. The AS2842/4 has UVLO thresholds of 16 volts (on) and 10 volts (off). The AS2843/5 has UVLO levels of 8.4 volts (on) and 7.6 volts (off). 1.2 Reference (VREG and VFB) The AS2842 effectively has two precise band gap based temperature compensated voltage references. Most obvious is the VREG pin (pin 8) which is the output of a series pass regulator. This 5.0 V output is normally used to provide charging current to the oscillator's timing capacitor (Section 1.3). In addition, there is a
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AS2842/3/4/5
trimmed internal 2.5 V reference which is connected to the non-inverting (+) input of the error amplifier. The tolerance of the internal reference is 0.5% over the full specified temperature range, and 1% for VREG. The reference section of the AS2842 is greatly improved over the standard 2842 in a number of ways. For example, in a closed loop system, the voltage at the error amplifier's inverting input (VFB, pin 1) is forced by the loop to match the voltage at the non-inverting input. Thus, V FB is the voltage which sets the accuracy of the entire system. The 2.5 V reference of the AS2842 is tightly trimmed for precision at VFB, including errors caused by the op amp, and is specified over temperature. This method of trim provides a precise reference voltage for the error amplifier while maintaining the original 5 V regulator specifications. In addition, force/sense (Kelvin) bonding to the package pin is utilized to further improve the 5 V load regulation. Standard 2842's, on the other hand, specify tight regulation for the 5 V output only and rate it over line, load and temperature. The voltage at VFB, which is of critical importance, is loosely specified and only at 25 C. The reference section, in addition to providing a precise DC reference voltage, also powers most of the IC's internal circuitry. Switching noise, therefore, can be internally coupled onto the reference. With this in mind, all of the logic within the AS2842 was designed with ECL type circuitry which generates less switching noise because it runs at essentially constant current regardless of logic state. This, together with improved AC noise rejection, results in substantially less switching noise on the 5 V output. The reference output is short circuit protected and can safely deliver more than 20 mA to power external circuitry.
47
AS2842/3/4/5
1.3 Oscillator The newly designed oscillator of the AS2842 is enhanced to give significantly improved performance. These enhancements are discussed in the following paragraphs. The basic operation of the oscillator is as follows: A simple RC network is used to program the frequency and the maximum duty ratio of the AS2842 output. See Figure 15. Timing capacitor (CT) is charged through timing resistor (RT) from the fixed 5.0 V at VREG. During the charging time, the OUT (pin 6) is high. Assuming that the output is not terminated by the PWM latch, when the voltage across CT reaches the upper oscillator trip point (3.0 V), an internal current sink from pin 4 to ground is turned on and discharges C T towards the lower trip point. During this discharge time, an internal clock pulse blanks the output to its low state. When the voltage across CT reaches the lower trip point (1.3 V), the current sink is turned off, the output goes high, and the cycle repeats. Since the output is blanked during the discharge of CT, it is the discharge time which controls the output deadtime and hence, the maximum duty ratio.
Current Mode Controller
The nature of the AS2842 oscillator circuit is such that, for a given frequency, many combinations of RT and CT are possible. However, only one value of RT will yield the desired maximum duty ratio at a given frequency. Since a precise maximum duty ratio clamp is critical for many power supply designs, the oscillator discharge current is trimmed in a unique manner which provides significantly improved tolerances as explained later in this section. In addition, the AS2844/5 options have an internal flip-flop which effectively blanks every other output pulse (the oscillator runs at twice the output frequency), providing an absolute maximum 50% duty ratio regardless of discharge time. 1.3.1 Selecting timing components RT and CT The values of RT and CT can be determined mathematically by the following expressions:
CT =
D K R T OSC ln L KH
=
1.63D R T OSC
(1)
7 VCC 8 CT 5 V REG PWM CLOCK 4 ID CT AS2842 OUTPUT Small RT/ Large CT 5 GND OSCILLATOR CT OUTPUT 6 OUTPUT Large RT/Small CT
RT
Figure 15. Oscillator Set-up and Waveforms
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Current Mode Controller
V (KL ) D - (KH ) D RT = REG 1- D 1- D ID ( K ) D - ( K ) D L H
1 1
AS2842/3/4/5
( 2)
1 D 1- D D
Table 1. RT vs Maximum Duty Ratio
RT () Dmax
470
22% 37% 50% 54% 58% 63% 66% 72% 77% 81% 85% 88% 90% 91% 93% 94% 95% 96% 97% 98%
= 582
(0.736) - (0.432)
1 D
560 683 750
(0.736)
1- D D
- (0.432)
KL = KH =
VREG - VL VREG VREG - VH VH
0.736 0.432
(3) ( 4)
820 910 1,000 1,200 1,500
where fosc is the oscillator frequency, D is the maximum duty ratio, VH is the oscillator's upper trip point, VL is the lower trip point, VR is the Reference voltage, ID is the discharge current. Table 1 lists some common values of RT and the corresponding maximum duty ratio. To select the timing components; first, use Table 1 or equation (2) to determine the value of RT that will yield the desired maximum duty ratio. Then, use equation (1) to calculate the value of CT. For example, for a switching frequency of 250 kHz and a maximum duty ratio of 50%, the value of R T, from Table 1, is 683 . Applying this value to equation (1) and solving for CT gives a value of 4700 pF. In practice, some fine tuning of the initial values may be necessary during design. However, due to the advanced design of the AS2842 oscillator, once the final values are determined, they will yield repeatable results, thus eliminating the need for additional trimming of the timing components during manufacturing. 1.3.2 Oscillator enhancements The AS2842 oscillator is trimmed to provide guaranteed duty ratio clamping. This means that the discharge current (ID ) is trimmed to a value
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1,800 2,200 2,700 3,300 3,900 4,700 5,600 6,800 8,200 10,000 18,000
that compensates for all of the tolerances within the device (such as the tolerances of V REG, propagation delays, the oscillator trip points, etc.) which have an effect on the frequency and maximum duty ratio. For example, if the combined tolerances of a particular device are 0.5% above nominal, then ID is trimmed to 0.5% above nominal. This method of trimming virtually eliminates the need to trim external oscillator components during power supply manufactur-
49
AS2842/3/4/5
ing. Standard 2842 devices specify or trim only for a specific value of discharge current. This makes precise and repeatable duty ratio clamping virtually impossible due to other IC tolerances. The AS2844/5 provides true 50% duty ratio clamping by virtue of excluding from its flipflop scheme, the normal output blanking associated with the discharge of CT. Standard AS2844/ 5 devices include the output blanking associated with the discharge of CT, resulting in somewhat less than a 50% duty ratio. 1.3.3 Synchronization The advanced design of the AS2842 oscillator simplifies synchronizing the frequency of two or more devices to each other or to an external clock. The RT/CT doubles as a synchronization input which can easily be driven from any open collector logic output. Figure 16 shows some simple circuits for implementing synchronization.
8 Open Collector Output VREG A 2842 4 RT/CT GND 5 CT Open Collector Output 3K RT
Current Mode Controller
1.4 Error amplifier (COMP) The AS2842 error amplifier is a wide bandwidth, internally compensated operational amplifier which provides a high DC open loop gain (90 dB). The input to the amplifier is a PNP differential pair. The non-inverting (+) input is internally connected to the 2.5 V reference, and the inverting (-) input is available at pin 2 (VFB). The output of the error amplifier consists of an active pulldown and a 0.8 mA current source pull-up as shown in Figure 17. This type of output stage allows easy implementation of soft start, latched shutdown and reduced current sense clamp functions. It also permits wire "OR-ing" of the error amplifier outputs of several 2842s, or complete bypass of the error amplifier when its output is forced to remain in its "pull-up" condition.
5V
CMOS RT/CT 2K
3K RT/CT 2K
SYNC
Figure 16. Synchronization
EXTERNAL CLOCK
1 COMP
From
VOUT
COMPENSATION NETWORK
E/A
0.8 mA
2 VFB
- +
TO PWM
2.50 V
Figure 17. Error Amplifier Compensation
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Current Mode Controller
In most typical power supply designs, the converter's output voltage is divided down and monitored at the error amplifier's inverting input, VFB. A simple resistor divider network is used and is scaled such that the voltage at VFB is 2.5 V when the converter's output is at the desired voltage. The voltage at VFB is then compared to the internal 2.5 V reference and any slight difference is amplified by the high gain of the error amplifier. The resulting error amplifier output is level shifted by two diode drops and is then divided by three to provide a 0 to 1 V reference (VE) to one input of the current sense comparator. The level shifting reduces the input voltage range of the current sense input and prevents the output from going high when the error amplifier output is forced to its low state. An internal clamp limits VE to 1.0 V. The purpose of the clamp is discussed in Section 1.5. 1.4.1 Loop compensation Loop compensation of a power supply is necessary to ensure stability and provide good line/load regulation and dynamic response. It is normally provided by a compensation network connected between the error amplifier's output (COMP) and inverting input as shown
80 240 210 Gain 60 Phase 40 180 150 Phase (Degrees) 120 90 20 60 30 0 0 -30 -20 101 -60 102 103 104 105 Frequency (Hz) 106 107
AS2842/3/4/5
in Figure 17. The type of network used depends on the converter topology and in particular, the characteristics of the major functional blocks within the supply - i.e. the error amplifier, the modulator/switching circuit, and the output filter. In general, the network is designed such that the converters overall gain/phase response approaches that of a single pole with a -20 dB/ decade rolloff, crossing unity gain at the highest possible frequency (up to f SW/4) for good dynamic response, with adequate phase margin (> 45) to ensure stability. Figure 18 shows the Gain/Phase response of the error amplifier. The unity gain crossing is at 1.2 MHz with approximately 57 C of phase margin. This information is useful in determining the configuration and characteristics required for the compensation network. One of the simplest types of compensation networks is shown in Figure 19. An RC network provides a single pole which is normally set to compensate for the zero introduced by the the output capacitor's ESR. The frequency of the pole (fP) is determined by the formula;
P =
1 2 R C
(5)
CF
Gain (dB)
VOUT RI
RF
RBIAS
- E/A +
To PWM
2.50 V
Figure 18. Gain/Phase Response of the AS2842
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Figure 19. A Typical Compensation Network
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AS2842/3/4/5
Resistors R1 and RF set the low frequency gain and should be chosen to provide the highest possible gain, without exceeding the unity gain crossing frequency limit of fSW /4. RBIAS, in conjunction with R1, sets the converter's output voltage; but has no effect on the loop gain/phase response. There are a few converter design considerations associated with the error amplifier. First, the values of the divider network (R1 and RBIAS) should be kept low in order to minimize errors caused by the error amplifier's input bias current ( -1.0 A). An output voltage error equal to the product of the input bias current and the equivalent divider resistance, can be quite significant with divider values greater than 5 k. Low divider resistor values also help to improve the noise immunity of the sensitive VFB input. The second consideration is that the error amplifier will typically source only 0.8 mA; thus, the value of feedback resistance (RF) should be no lower than 5 k in order to maintain the error amplifier's full output range. In practice, however, the feedback resistance required is usually much greater than 5 k, hence this limitation is normally not a problem. Some power supply topologies may require a more elaborate compensation network. For example, flyback and boost converters operating with continuous current have transfer functions that include a right half plane (RHP) zero. These types of systems require an additional pole element within the compensation network. A detailed discussion of loop compensation, however, is beyond the scope of this application note. 1.5 ISENSE current comparator/PWM latch The current sense comparator (sometimes called the PWM comparator) and accompanying latch circuitry make up the pulse width modulator (PWM). It provides pulse-by-pulse current
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Current Mode Controller
sensing/limiting and generates a variable duty ratio pulse train which controls the output voltage of the power supply. Included is a high speed comparator followed by ECL type logic circuitry which has very low propagation delays and switching noise. This is essential for high frequency power supply designs. The comparator has been designed to provide guaranteed performance with the current sense input below ground. The PWM latch ensures that only one pulse is allowed at the output for each oscillator period. The inverting input to the current sense comparator is internally connected to the level shifted output of the error amplifier (VE) as discussed in the previous section. The non-inverting input is the ISENSE input (pin 3). It monitors the switched inductor current of the converter. Figure 20 shows the current sense/PWM circuitry of the AS2842, and associated waveforms. The output is set high by an internal clock pulse and remains high until one of two conditions occur; 1) the oscillator times out (Section 1.3 )or 2) the PWM latch is set by the current sense comparator. During the time when the output is high, the converter's switching device is turned on and current flows through resistor R S. This produces a stepped ramp waveform at pin 3 as shown in Figure 20. The current will continue to ramp up until it reaches the level of V E at the inverting input. At that point, the comparator's output goes high, setting the PWM latch and the output pulse is then terminated. Thus, V E is a variable reference for the current sense comparator, and it controls the peak current sensed by RS on a cycle-by-cycle basis. VS varies in proportion to changes in the input voltage/current (inner control loop) while VE varies in proportion to changes in the converters output voltage/ current (outer control loop). The two control loops merge at the current sense comparator, producing a variable duty ratio pulse train that controls the output of the converter.
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Current Mode Controller
AS2842/3/4/5 1 COMP ERROR AMP + 2.5 V 2 VFB PWM COMPARATOR VE - + CURRENT SENSE RT/CT CLOCK - 2R R S R GND 5 5 V REG VCC PRI 7 SEC VREG VIN 8
AS2842/3/4/5
1V 3
PWM LOGIC FF OUTPUT 6 CLOCK VE VS OUTPUT IS
4 VS C
R Leadong Edge Filter
RS
Figure 20. Current Sense/PWN Latch Circuit and Waveforms
The current sense comparator's inverting input is internally clamped to a level of 1.0 V to provide a current limit (or power limit for multiple output supplies) function. The value of RS is selected to produce 1.0 V at the maximum allowed current. For example, if 1.5 A is the maximum allowed peak inductor current, then RS is selected to equal 1 V/1.5 A = 0.66 . In high power applications, power dissipation in the current sense resistor may become intolerable. In such a case, a current transformer can be used to step down the current seen by the sense resistor. See Figure 21.
N :1 VS VS =
1.6 Output (OUT) The output stage of the AS2842 is a high current totem-pole configuration that is well suited for directly driving power MOSFETs. It is capable of sourcing and sinking up to 1 A of peak current. Cross conduction losses in the output stage have been minimized resulting in lower power dissipation in the device. This is particularly important for high frequency operation. During undervoltage shutdown conditions, the output is active low. This eliminates the need for an external pulldown resistor. 1.7 Over-temperature shutdown The AS2842 has a built-in over-temperature shutdown which will limit the die temperature to 130 C typically. When the over-temperature condition is reached, the oscillator is disabled. All other circuit blocks remain operational. Therefore, when the oscillator stops running, output pulses terminate without losing control of the supply or losing any peripheral functions that may be running off the 5 V regulator. The output may go high during the final cycle, but the PWM
( IN ) R
S
S
RS
IS
Figure 21. Optional Current Transformer
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AS2842/3/4/5
latch is still fully operative, and the normal termination of this cycle by the current sense comparator will latch the output low until the overtemperature condition is rectified. Cycling the power will reset the over-temperature disable mechanism, or the chip will re-start after cooling through a nominal hysteresis band. Section 2 - Design Considerations 2.1 Leading edge filter The current sensed by RS contains a leading edge spike as shown in Figure 20. This spike is caused by parasitic elements within the circuit including the interwinding capacitance of the power transformer and the recovery characteristics of the rectifier diode(s). The spike, if not properly filtered, can cause stability problems by prematurely terminating the output pulse. A simple RC filter is used to suppress the spike. The time constant should be chosen such that
VE I L2
1
Current Mode Controller
it approximately equals the duration of the spike. A good choice for R1 is 1 k, as this value is optimum for the filter and at the same time, it simplifies the determination of R SLOPE (Section 2.2). If the duration of the spike is, for example, 100 ns, then C is determined by:
C=
Time Constant 1 k 100 ns = 1 k = 100 pF
(6)
2.2 Slope compensation Current-mode controlled converters can experience instabilities or subharmonic oscillations when operated at duty ratios greater than 50%. Two different phenomena can occur as shown
IPK IAVG 2 IAVG 1
VE I I'
m
IL1
T0
D1 (a)
D2
T1
T0
m
2
1
m
m
2
D1 (b)
D2
T1
VE
m=m
VE
m=m
2 /2
m
1
2 /2
m
1
I L2 IL1 IAVG 1 = IAVG 2
m
2
I
M
I'
2
T0
D1 (c)
D2
T1
T0
D1 (d)
D2
T1
Figure 22. Slope Compensation
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Current Mode Controller
graphically in Figure 22. First, current-mode controllers detect and control the peak inductor current, where as the converter's output corresponds to the average inductor current. Figure 22(a) clearly shows that the average inductor current (I1 & I2) changes as the duty ratio (D1 & D2) changes. Note that for a fixed control voltage, the peak current is the same for any duty ratio. The difference between the peak and average currents represents an error which causes the converter to deviate from true current-mode control. Second, Figure 22(b) depicts how a small perturbation of the inductor current (I) can result in an unstable condition. For duty ratios less than 50 %, the disturbance will quickly converge to a steady state condition. For duty ratios greater than 50 %, I progressively increases on each cycle, causing an unstable condition. Both of these problems are corrected simultaneously by injecting a compensating ramp into either the control voltage (VE) as shown in Figure 22(c) & (d), or to the current sense waveform at pin 3. Since VE is not directly accessible, and, a positive ramp waveform is readily available from
8 RT 4 RT/CT AS2842 IS RSLOPE R1 RS CT 3I SENSE GND 5 RS OPTIONAL BUFFER IS RSLOPE R1 VREG RT
AS2842/3/4/5
the oscillator at pin 4, it is more practical to add the slope compensation to the current waveform. This can be implemented quite simply with the addition of a single resistor, RSLOPE, between pin 4 and pin 3 as shown in Figure 23(a). RSLOPE, in conjunction with the leading edge filter resistor, R1 (Section 2.1), forms a divider network which determines the amount of slope added to the waveform. The amount of slope added to the current waveform is inversely proportional to the value of RSLOPE. It has been determined that the amount of slope (m) required is equal to or greater than 1/2 the downslope (m2) of the inductor current. Mathematically stated:
m
m2 2
(7)
In some cases the required value of R SLOPE may be low enough to affect the oscillator circuit and thus cause the frequency to shift. An emitter follower circuit can be used as a buffer for R SLOPE as depicted in Figure 23(b). Slope compensation can also be used to improve noise immunity in current mode converters operating at less than 50% duty ratio. Power supplies
8
VREG
4
RT/CT AS2842
CT 3I SENSE GND 5
(a)
(b)
Figure 23. Slope Compensation
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AS2842/3/4/5
operating under very light load can experience instabilities caused by the low amplitude of the current sense ramp waveform. In such a case, any noise on the waveform can be sufficient to trip the comparator resulting in random and premature pulse termination. The addition of a small amount of artificial ramp (slope compensation) can eliminate such problems without drastically affecting the overall performance of the system. 2.3 Circuit layout and other considerations The electronic noise generated by any switchmode power supply can cause severe stability problems if the circuit is not layed-out (wired) properly. A few simple layout practices will help to minimize noise problems. When building prototype breadboards, never use plug-in protoboards or wire wrap construction. For best results, do all breadboarding on double sided PCB using ground plane techniques. Keep
Current Mode Controller
all traces and lead lengths to a minimum. Avoid large loops and keep the area enclosed within any loops to a minimum. Use common point grounding techniques and separate the power ground traces from the signal ground traces. Locate the control IC and circuitry away from switching devices and magnetics. Also, the timing capacitor's ground connection must be right at pin 5 as shown in Figure 15. These grounding and wiring techniques are very important because the resistance and inductance of the traces are significant enough to generate noise glitches which can disrupt the normal operation of the IC. Also, to provide a low impedance path for high frequency noise, V CC and V REF should be decoupled to IC ground with 0.1 F capacitors. Additional decoupling in other sensitive areas may also be necessary. It is very important to locate the decoupling capacitors as close as possible to the circuit being decoupled.
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